This invention relates to a high speed bias voltage generating circuit and more particularly, to a high speed bias voltage generating circuit that may be adapted for use with a semiconductor device, that quickly generates a stable bias voltage in response to an input signal, and that consumes substantially no power when operating in a standby mode.
Bias voltage generating circuits or xe2x80x9cbias circuitsxe2x80x9d are typically used within semiconductor devices to provide bias voltages that are less than a supply voltage (e.g., Vcc or Vdd). Such bias voltages are often necessary to control or operate certain circuit elements or portions within semiconductor devices. By way of example, bias voltage generating circuits may be used within flash memory devices to drive word lines within the devices.
In order for the circuit elements or portions to respond and operate properly, it is desirable for bias circuits to generate a bias voltage rapidly (e.g., in response to an input signal changing value) and precisely. It is further desirable for bias circuits to have fast settling times (i.e., to provide bias voltages that stabilize in a very short period of time), and to consume little or no power while operating in a standby mode (i.e., when not providing the bias voltage).
There is therefore a need for a new and improved bias voltage generating circuit for use with semiconductordevices, which provides a relatively fast response and settling time, and which consumes substantially no power when operating in a standby mode.
A first non-limiting advantage of the invention is that it provides a high speed bias voltage generating circuit for use with semiconductor devices.
A second non-limiting advantage of the invention is that it provides a high speed bias voltage generating circuit having a very fast response and settling time.
A third non-limiting advantage of the invention is that it provides a high speed bias voltage generating circuit that consumes substantially no power while operating in a standby mode.
According to a first aspect of the present invention, a high speed bias voltage generating circuit is provided. The circuit includes a first node for receiving an input signal; a second node for providing an output voltage; -and first, second and third circuits. The first circuit is coupled to the first node and the second node, and is adapted to provide a standby. voltage and substantially: no output current to the second node when the input signal has a first value. The second circuit is coupled to the first node and the second node, and is adapted to provide a bias voltage to the second node when the input signal has a second value different from the first value. The third circuit is coupled to the first node and to the second node, and is, adapted to cause the output voltage to be rapidly lowered from the standby voltage to a value close to the bias voltage after the input signal switches from the first value to the second value.
According to a second aspect of the present invention, a high speed bias voltage generating circuit is provided. The circuit includes an input terminal that provides an input signal; an output terminal that receives an output signal; a standby circuit portion which is coupled to the input and output terminals, which is active only when the input signal has a first value, and which-is adapted to provide a standby voltage at the output terminal when active; a bias circuit portion which is coupled to the input and output terminals, which is active only when the input signal has a second value different from the first value, and which is adapted to provide a bias voltage at the output terminal when active; and a boost circuit portion which is coupled to the input and output terminals, which is active only during a predetermined period of time after the input signal switches from the first value to the second value, and which is adapted to cause the output voltage to rapidly approach the bias voltage during the predetermined period of time.
According to a third aspect of the present invention, a method is disclosed for providing a bias voltage in response to an input signal. The method includes the steps of: providing a standby voltage at an output node by use of a first circuit when the input signal has a first value; providing a bias voltage at the output node by use of a second circuit when the input signal has a second value and quickly -lowering the voltage at the output node from the standby voltage to the bias voltage by use of a third circuit, when the input signal switches from the first value to the second value.
These and other features, advantages, and objects of the invention will become apparent by reference to the following specification and by reference to the following drawings.